Online VHDL training (2023)

FirstEDA provides high quality live instructor-led training, on-site and online, in language and methodology as well as tool skills. Our interactive courses and seminars are developed and delivered by our experienced engineers or through our long-term partnership with SynthWorks' industry-renowned VHDL expert, Jim Lewis, who is an active contributor to the IEEE VHDL standard and open source VHDL verification methodology.OSVVM),.

Our past and present engineering experience adds enormous value to all our courses and ensures that the live VHDL training you receive face-to-face and online is fit for purpose. For example, we can teach you the best coding techniques and guide you on how to formalize the verification process; all this helps shorten project deadlines.

Our VHDL courses are interesting, practical and social, and we certainly haven't lost sight of the fact that engineering can be both fun and useful. Whether you're learning new skills or improving existing ones, you'll network with like-minded people who are passionate about learning new technologies and approaches to advance your career.

All of our face-to-face interactive online courses include 50/50 lectures and lab exercises. See details andOnline and onsite VHDL training programsunder.

Why choose First EDA??

  • Our face-to-face and live online VHDL courses are taught by senior engineers with over 60 years of combined industry experience
  • We can provide you with live, face-to-face or online training and tailor the course content to meet all your specific requirements
  • Our live online courses are cost effective and highly rated

"The importance of keeping engineering skills up to date and learning the right methods cannot be emphasized enough. After many years with FirstEDA, I have seen hundreds of engineers complete our courses and return inspired and enthusiastic about their organization."Jim Lewis, SynthWorks.

VHDL is a hardware description language (HDL) used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays (FPGAs) and integrated circuits (ICs). VHDL is an acronym for VHSIC (Very High Speed ​​Integrated Circuit) hardware description language.

The latest ASIC and FPGA Functional Verification Survey by Wilson Research Group shows that more than 60% of FPGA designs worldwide use VHDL. In Europe, this figure is even higher. VHDL is a deterministic, highly self-checking language, and as such, HDL is the choice for avionics and Milaero, and anyone designing safety-critical and high-reliability systems. VHDL is also the latest HDL that can be used for design and verification without switching to confusing object-oriented verification techniques.

As a European company supporting European customers, we work on VHDL. We offer three language and methodological courses:VHDL for FPGA Designers(provides a comprehensive background on writing, using, and applying synthesizable VHDL);Between VHDL(to push the app further) iAdvanced VHDL test bench and verification(AKA "OSVVM Boot Camp", covering transaction-level modeling, introspection, functional coverage, and limited random testbenches).

Our personal and online live training

VHDL for FPGA Designers(3 days online)

Our introductory VHDL course provides a comprehensive background in the use and application of VHDL in digital hardware design.

The training is built around a set of basic components to demonstrate the use of VHDL.

This first part of our online VHDL training series covers the fundamental concepts and syntax related to the circuit structures covered and provides FPGA designers with sufficient knowledge to begin writing synthesizable VHDL upon successful completion of the course. We also offer additional VHDL courses that cover more advanced language constructs and methods.

Advantages of the course:

  • Provides a solid understanding of basic VHDL concepts
  • It introduces you to syntax and language blocks that are based on many common assembly elements
  • It gives you hands-on experience writing and verifying simple VHDL designs

For full course details and dates, seeOnline VHDL course plan.

Between VHDL(5 days online)

Are you ready for the next step? For those already familiar with VHDL (either through an introductory course or self-study), this VHDL course will expand knowledge and build competence through application.

This online, instructor-led intermediate VHDL course is designed to bridge the gap between a basic knowledge of VHDL and our advanced VHDL verification and testing courses. All our courses are taught by experienced engineers whose experience goes far beyond theory.

Advantages of the course:

  • Provides hands-on experience writing, testing and synthesizing VHDL code and how to implement it on an FPGA
  • Improve your current understanding of VHDL with challenging hardware coding questions
  • Introduction of a transaction-based testing platform
  • Introduction to FSM coding techniques
  • VHDL hardware erfaring med FPGA lab board

Each delegate will receive an FPGA development card that can be used during lab exercises or after the course to further expand their VHDL knowledge.

For full course details and dates, seeOnline VHDL course plan.

Advanced VHDL test bench and verification

(10 days online) (5 days live)

Our advanced in-person and online VHDL courses teach the latest VHDL verification techniques and methods for FPGAs and ASICs, includingOpen source VHDL verification method(OSVVM).

You will gain the knowledge needed to increase verification productivity and create a VHDL test environment that competes with other verification languages ​​such as SystemVerilog (UVM).

Unlike UVM, our approach works with any simulator that supports VHDL-2008 without you having to learn a new language or invest in new expensive tools.

Developed and provided by Jim Lewis, Chair of the IEEE VHDL Standards Working Group and Principal Architect of OSVVM.

This training can be held as a comprehensive course (Advanced VHDL test bench and verification), or in two parts, as indicated below:

1. dio:Basic VHDL Verification(6 days online) (3 days live)

You learn to create a structured transactional test bed using procedures or models (aka: verification IP or transaction-level models). Both approaches help create simple, robust, and readable tests.

Advantages of the course:

  • Structural transaction infrastructure using OSVVM
  • Type OSVVM Verification IP
  • Simplify test writing with interface transactions (CpuRead, CpuWrite)
  • Add error injection to interface transaction
  • Implement test plans to increase reuse from RTL to kernel to system level tests
  • Write directed, algorithmic, constrained random, and intelligently covered random tests
  • Write functional coverage to track your test requirements (test plan)
  • Simplify error reporting with OSVVM's alert and confirmation tools
  • Simplify the printing of conditional messages (eg debugging) using OSVVM's logging tool
  • Add a self-check to the test
  • Generic semaphore and FIFO using OSVVM
  • Use the OSVVM synchronization tools (WaitForBarrier, WaitForClock, etc.)
  • Analog values ​​and periodic wave models
  • Take advantage of OSVVM's growing library of open source verification IPs

2. dio:Professional VHDL verification(4 days online) (2 days live)

VHDL Expert Check builds on the fundamental topics covered in Basic VHDL Check and teaches advanced topics including multithreaded modeling (such as AXI4-Lite), advanced function coverage, advanced randomization, creating data structures with protected types and accessor types, timing and execution , configuration and modeling of RAM.

Advantages of the course:

  • Write complex multi-threaded control components such as AXI-Lite
  • Use the configuration to control the execution of the tests
  • Check the self-test model
  • Write an AXI Stream master-slave model
  • Write a model with interrupt handling functions
  • Simplified implementation of the memory model using OSVVM's MemoryPkg,
  • Type of write protection and type of access
  • Understanding of VHDL execution and timing
  • Advanced overlay and randomization techniques

For full course details and dates, seeSchedule for online and on-site VHDL courses.

For all the above courses, delegates will receive high quality material including lecture notes and detailed lab books (supporting all material covered during the course). For remote online courses, course materials and software licenses will be delivered prior to the course start date. The course is approximately 50/50 lectures and exercises, so there is plenty of opportunity to strengthen the theory.

Live online classes and face-to-face class schedules


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